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 PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FEATURES
* Two LVCMOS/LVTTL outputs, 15 typical output impedance * Crystal oscillator interface * Output frequency range: 75MHz and 106.25MHz, or 212.5MHz * RMS phase jitter at 106.25MHZ (637kHz - 5MHz): 0.86ps (typical) * Full 3.3V or 3.3V core/2.5V output supply mode * 0C to 70C ambient operating temperature
GENERAL DESCRIPTION
The ICS840002-32 is a 2 output LVCMOS/ LVTTL Synthesizer optimized to generate HiPerClockSTM Fibre Channel or Serial ATA reference clock frequencies and is a member of the HiPerClocks TM family of high perfor mance clock solutions from ICS. Using an 18pF parallel resonant crystal, the following frequencies can be generated based on 1 frequency select pin (SEL): 106.25MHz and 75MHz, or 212.5MHz. The ICS840002-32 uses ICS' 3 rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Fibre Channel and Serial ATA jitter requirements. The ICS840002-32 is packaged in a small 8-pin TSSOP package.
ICS
SELECT FUNCTION TABLE
Input SEL 0 1 Output Frequency Range (MHz) Q0 75 75 Q1 106.25 212.5
BLOCK DIAGRAM
26.5625MHz
PIN ASSIGNMENT
Q0
XTAL_IN
FemtoClockTM
XTAL_OUT Q1
VDD XTAL_OUT XTAL_IN GND
1 2 3 4
8 7 6 5
SEL Q0 VDDO Q1
ICS840002-32
SEL
8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840002BG-32 www.icst.com/products/hiperclocks.html REV. A JUNE 27, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Type Power Input Power Output Power Input Description Core supply pin. Cr ystal oscillator interface. Power supply ground. Single-ended clock outputs. LVCMOS/LVTTL interface levels. 15 typical output impedence. Output supply pin. Pulldown Select pin. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1 2, 3 4 5, 7 1 8 Name VDD XTAL_OUT, XTAL_IN GND Q1, Q0 VDDO SEL
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance Input Pulldown Resistor Output Impedance VDD, VDDO = 3.465V VDD = 3.465V, VDDO = 2.625V Test Conditions Minimum Typical 4 TBD TBD 51 15 Maximum Units pF pF pF k
840002BG-32
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REV. A JUNE 27, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
4.6V -0.5V to VDD + 0.5 V -0.5V to VDDO + 0.5V 101.7C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 TBD TBD Maximum 3.465 3.465 Units V V mA mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 TBD TBD Maximum 3.465 2.625 Units V V mA mA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol Parameter VIH VIL IIH IIL VOH VOL Input High Voltage Input Low Voltage Input High Current Input Low Current SEL SEL SEL SEL VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDDO = 3.3V 5% VDDO = 2.5V 5% VDDO = 3.3V or 2.5V 5% -150 2.6 1.8 0.5 Test Conditions Minimum Typical 2 -0.3 Maximum VDD + 0.3 0.8 5 Units V V A A V V V
Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal.
840002BG-32 www.icst.com/products/hiperclocks.html REV. A JUNE 27, 2005
Test Conditions
Minimum
Typical 26.5625
Maximum
Units MHz
Fundamental 50 7 1 pF mW
3
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
Test Conditions Minimum Typical 212.5 106.25 75 TBD 212.5MHz @ Integration Range: 2.55MHz - 20MHz 106.25MHz @ Integration Range: 637kHz - 5MHz 75MHz @ Integration Range: 12kHz - 20MHz 20% to 80% 0.50 0.86 TBD 400 ps ps ps ps ps % Maximum Units MHz
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Range Output Skew; NOTE 1, 3
tsk(o)
tjit(O)
RMS Phase Jitter (Random); NOTE 2
t R / tF
Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 2.5V5%, TA = 0C TO 70C
Symbol fOUT Parameter Output Frequency Range Output Skew; NOTE 1, 3 212.5MHz @ Integration Range: 2.55MHz - 20MHz 106.25MHz @ Integration Range: 637kHz - 5MHz 75MHz @ Integration Range: 12kHz - 20MHz 20% to 80% Test Conditions Minimum Typical 212.5 106.25 75 TBD 0.57 1.1 TBD 450 ps ps ps ps ps % Maximum Units MHz
tsk(o)
tjit(O)
RMS Phase Jitter (Random); NOTE 2
tR / tF
Output Rise/Fall Time
odc Output Duty Cycle 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at VDDO/2. NOTE 2: Please refer to the Phase Noise Plot. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
840002BG-32
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REV. A JUNE 27, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
1.65V5% 2.05V5% 1.25V5%
VDD, VDDO
SCOPE
Qx
V DD VDDO
SCOPE
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
V
Qx
Phase Noise Mask
DDO
2
V
Qy
f1 Offset Frequency f2
DDO
2 tsk(o)
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT SKEW
V
80% 20% tR
80%
Q0, Q1
DDO
2
Clock Outputs
20% tF
t PW
t
PERIOD
odc =
t PW t PERIOD
x 100%
OUTPUT RISE/FALL TIME
840002BG-32
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
www.icst.com/products/hiperclocks.html REV. A JUNE 27, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS840002-32 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 1 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p
ICS840002-32
Figure 1. CRYSTAL INPUt INTERFACE
RELIABILITY INFORMATION
TABLE 6. JAVS. AIR FLOW TABLE
FOR
8 LEAD TSSOP
JA by Velocity (Meters Per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 101.7C/W
1
90.5C/W
2.5
89.8C/W
TRANSISTOR COUNT
The transistor count for ICS840002-32 is: 2322
840002BG-32
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REV. A JUNE 27, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
FOR
PACKAGE OUTLINE - G SUFFIX
8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 2.90 6.40 BASIC 4.50 Millimeters Minimum 8 1.20 0.15 1.05 0.30 0.20 3.10 Maximum
Reference Document: JEDEC Publication 95, MO-153
840002BG-32 www.icst.com/products/hiperclocks.html REV. A JUNE 27, 2005
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS840002-32
FEMTOCLOCKSTMCRYSTAL-TOLVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS840002BG-32 ICS840002BG-32T Marking 02B32 02B32 Package 8 lead TSSOP 8 lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature 0C to 70C 0C to 70C
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 840002BG-32
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REV. A JUNE 27, 2005


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